In any low-noise circuit, the performance of the 1st-stage is most critical.

Consider this circuit:

The 1st-stage is built of discrete matched-pair NPN transistors (bipolar devices are generally much quieter than MOS devices). The MAT02 devices were originally built by Precision Monolithics (PMI) which was one of my favorite analog semiconductor suppliers … but that’s a different story.

The part is now provided by Analog Devices – although just as I write this I saw that this part is now – 25 years later – entered End-of-Life status. It is being replaced by the MAT12 which is in pre-production and given that the supplier is Analog Devices, I am sure that the new part is at least as good and probably better than the old.

Another oldie-but-goodie is Linear Technology’s LT1028A op-amp … noise characteristics being dependent on source resistance, I can’t state that this is the “best” low-noise op-amp, but it’s certainly on the “must consider” list.

The discrete resistors should be relatively low-value metal-film – RN types being among those that should be considered. While integrated resistors have the advantage of size and matching, they generally have noisy parasitics and handle less power … keep in mind I’m emphasizing noise performance.

This will be a 1st-order design guide. High-precision applications will require a more detailed analysis and careful layout and construction. Temperature effects are at least commonly thought of – a controlled environment is necessary to maximize noise performance – but ambient light also causes an increase in noise. The circuit should be mounted in a light-tight enclosure.

The current source can also be improved. Cascoding the existing mirror with another pair of MAT02s would be a 1st step.

R1, R2, Q1a, and Q1b form a differential-input, differential output amplifier. The network of R3 and Q2 form a simple current mirror: Q2b provides a bias current to the amplifier and R3 and Q2a control the current level.

The amplifier structure consists of two common-emitter stages. As such, the gain can be calculated as:

where

“T” is temperature in degrees Kelvin (K). 0°C = 273.15K

“k” is Boltzman’s Constant and has a value of 1.3806504E-23 J/K^[1]

“q” is electron charge and has a value of 1.6021765E-19 C

Now I like to use a slightly elevated temperature for these kind of calculations. The equation refers to the junction temperature and a junction with even light current will be hotter than “ambient” – although this is somewhat nebulous anyway. I generally use 40°C for “normal” temperature – and drop the “0.15″ part of the temperature. This makes the thermal voltage…

Another way of looking at this expression is:

where the temperature effect is explicitly stated

The gain of the differential amplifier can be found to be:

The usual assumptions are that V_T,1 = V_T,2, I_C,1 = I_C,2, and R₁ = R₂. In this situation, the gain is simply

So what are the necessary conditions to meet these three assumptions?

I_C,1 = I_C,2 (At bias point)
Layout will have a large effect on this. Assuming a symmetrical and matched layout – and identical loads (both Q and R), the current will split into each branch identically. Differences in resistance of the emitter legs may create an imbalance due to differences in emitter degeneration, but as the transistors are matched and in the same package, this shouldn’t be a problem. This being a low-impedance node, small differences in resistance could add error. This node is assumed to be at AC ground.

V_T,1 = V_T,2
The only variable here is temperature. A 0.3°C difference between Q1a and Q1b will create a 0.1% error: 1 bit in a 10-bit system. The packaging is such that any temperature difference will be due to current differences in the junctions. This is a major reason for using matched transistor pairs rather than two separate discrete devices.

R₁ = R₂
This is actually the most difficult of the three to achieve. It is preferred that the devices be electrically separated but they need to be matched in both absolute value and temperature coefficient … difficult to do with discrete devices. The resistor values can be matched if necessary but matching tempcos is more difficult. Hence the need for more detailed analysis if applied to a precision application.

The value of a resistor to 1st-order (2nd-order figures are likely not available) is

where ΔT is the difference between the actual resistor temperature and the manufacturer’s reference temperature – usually 25°C or 27°C. The resistor isn’t subject to the same heating issues as the transistors, so here the ambient temperature should be used. (Note: this can sometimes create problems in simulators that don’t allow for differing temperatures within a circuit)

A voltage dependency in a resistor is a secondary effect that shouldn’t be an issue here, but is mentioned to cover bases. The topology shouldn’t permit a voltage difference significant enough to be an issue, but again, a precision application will require deeper analysis.

An imbalance in resistance causes an degradation of the common-mode rejection ration (CMRR) which is a measure of the ability of a differential amplifier to reject common-mode signals while amplifying differential signals. Because R is generally large compared to the parasitic resistances due to wiring and layout, the main concern is with temperature. This issue is best addressed by placing the resistors in close physical proximity – touching but electrically isolated is ideal.

Vishay sells a CMF55/RN55 1/8W discrete resistor with a tempco of 25ppm available in 0.1% tolerance (“E”) and a voltage coefficient of 5ppm between 20V and the full rated voltage of 200V. The main disadvantage is the material is NiCr which could possibly be a problem in magnetic-field sensing circuits.

The inputs are medium-impedance nodes. Because of the finite bias currents in bipolar devices, a voltage is developed at each input. This is more an issue with the circuitry connected to the input which is effectively connected to an infinite input impedance. This network prefers a low-impedance drive at the input. The input parasitic effects in this network are of minimal concern.

Current Source
A controlled bias current source is desired for this topology. The collector of Q2b supplies a common-mode current whose perturbations are rejected as common-mode signals (common to both sides of the differential pair).

A caveat: common-mode rejection is frequency-dependent. At 60dB rejection, the common-mode signal represents 1-bit of a 10-bit system

In this topology a significant degree of common-mode rejection occurs in the first stage, but the 2nd-stage provides a much higher degree.

The current source is a simple mirror network. Q2a is forced to have equal V_BE and V_CE which forces an identical I_C (I_C = β I_B) in Q2b. Unfortunately, it does not force identical V_CE which is necessary for proper matching. On the other hand, a varying V_CE allows a range of common-mode voltages. Therefore, it is desirable to have a high Thevenin equivalent resistance which would require more sophisticated networks than shown here.

The differential output is fed to a high-quality, low-noise op-amp which provides differential-to-single-ended conversion. This stage also adds additional gain, increases common-mode rejection, and output drive capability. The open-loop gain the the product of both stages; in this configuration, the system gain is controlled by resistors R4 and R5. The LT1028A is manufactured by Linear Technology and is still an active part.

I believe it’s time for some numbers … and that makes a good break point for a new page.

Next: Numbers

Previous: Introduction

[1] Values for physical constants (and other interesting things) come from NIST